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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. lp3907 snvs511s ? june 2007 ? revised april 2016 lp3907 dual high-current step-down dc-dc and dual linear regulator with i 2 c interface 1 1 features 1 ? input voltage range: 2.8 v to 5.5 v ? compatible with advanced applications processors and fpgas ? 2 ldos for powering internal processor functions and i/os ? high-speed serial interface for independent control of device functions and settings ? precision internal reference ? thermal overload protection ? current overload protection ? software programmable regulators ? external power-on-reset function for buck1 and buck2 (power good with delay function) ? undervoltage lockout detector to monitor input supply voltage ? step-down dc-dc converter (buck) ? programmable v out from: ? buck1 : 0.8 v ? 2 v at 1 a ? buck2 : 1 v ? 3.5 v at 600 ma ? up to 96% efficiency ? 2.1-mhz pwm switching frequency ? pwm-to-pfm automatic mode change under low loads ? 3% output voltage accuracy ? automatic soft start ? linear regulators (ldo) ? programmable v out of 1 v to 3.5 v (except jj11 , fx6w , and jx6x options) ? 3% output voltage accuracy ? 300-ma output current ? 30-mv (typical) dropout 2 applications ? fpga, dsp core power ? applications processors ? peripheral i/o power ? hearing aids ? electronic measurement units ? equipment run-off of battery backup 3 description the lp3907 is a multi-function, programmable power management unit (pmu) optimized for low-power fpgas, microprocessors, and dsps. this device integrates two highly efficient 1-a/600-ma step-down dc-dc converters with dynamic voltage management (dvm), two 300-ma linear regulators, and a 400-khz i 2 c interface to allow a host controller access to the internal control registers of the device. the lp3907 additionally features programmable power-on sequencing. device information (1) part number package body size lp3907 wqfn (24) 4.00 mm 4.00 mm (nom) dsbga (25) 2.521 mm 2.521 mm (max) (1) for all available packages, see the orderable addendum at the end of the data sheet. typical application circuit lp3907 vinldo1 sda gnd_l ldo1 enldo1 scl vin1 ldo2 sw2 fb2 vin2 gnd_sw2 ensw1 ensw2 vinldo2 en_t enldo2 gnd_c avdd vinldo12 dap 0.47 p f 1 p f 1 p f 0.47 p f 2.2 p h 10 p f 10 p f 1 p f 1 p f 10 p f gnd_sw1 sw1 fb1 10 p f 2.2 p h npor vdd 100k copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison tables ................................... 3 6 pin configuration and functions ......................... 4 7 specifications ......................................................... 6 7.1 absolute maximum ratings ...................................... 6 7.2 esd ratings .............................................................. 6 7.3 recommended operating conditions (bucks) .......... 6 7.4 thermal information .................................................. 7 7.5 general electrical characteristics ............................ 7 7.6 low dropout regulators, ldo1 and ldo2 ............. 8 7.7 buck converters sw1, sw2 .................................... 8 7.8 i/o electrical characteristics .................................... 9 7.9 power-on reset (por) threshold/function .......... 9 7.10 i 2 c interface timing requirements ....................... 9 7.11 typical characteristics ? ldo ............................. 10 7.12 typical characteristics ? bucks .......................... 12 7.13 typical characteristics ? buck1 .......................... 13 7.14 typical characteristics ? buck2 .......................... 14 7.15 typical characteristics ? bucks .......................... 15 8 detailed description ............................................ 17 8.1 overview ................................................................. 17 8.2 functional block diagram ....................................... 17 8.3 feature description ................................................. 18 8.4 device functional modes ........................................ 26 8.5 programming .......................................................... 27 8.6 register maps ........................................................ 30 9 application and implementation ........................ 40 9.1 application information ............................................ 40 9.2 typical application ................................................. 40 10 power supply recommendations ..................... 46 10.1 analog power signal routing ............................... 46 11 layout ................................................................... 47 11.1 dsbga layout guidelines .................................... 47 11.2 layout example .................................................... 48 11.3 thermal considerations of wqfn package ......... 48 12 device and documentation support ................. 49 12.1 documentation support ........................................ 49 12.2 trademarks ........................................................... 49 12.3 community resources .......................................... 49 12.4 electrostatic discharge caution ............................ 49 12.5 glossary ................................................................ 49 13 mechanical, packaging, and orderable information ........................................................... 49 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision r (may 2015) to revision s page ? added additional items to applications .................................................................................................................................. 1 ? changed symbol " n " to " e n " in low dropout regulators, ldo1 and ldo2 electrical char table ....................................... 8 changes from revision q (january 2015) to revision r page ? added last sentence to " note " .......................................................................................................................................... 21 changes from revision p (november 2014) to revision q page ? changed to new default device options table with updated and additional values .............................................................. 3 ? changed handling ratings table to esd ratings table ........................................................................................................ 6 ? added updated thermal information ..................................................................................................................................... 7 changes from revision o (may 2013) to revision p page ? added device information and handling rating tables, feature description , device functional modes , application and implementation , power supply recommendations , layout , device and documentation support , and mechanical, packaging, and orderable information sections; moved some curves to application curves section .............. 1
3 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 5 device comparison tables table 1. default i 2 c addresses package type default i 2 c address 24-lead wqfn 60 25-bump dsbga 61 (1) vin+ is the largest potential voltage on the device. table 2. power block power block input power block operation note enabled disabled vinldo12 vin+ (1) vin+ always powered avdd vin+ vin+ always powered vin1 vin+ vin+ vin2 vin+ vin+ ldo1 vin+ vin+ if enabled, minimum v in is 1.74 v ldo2 vin+ vin+ if enabled, minimum v in is 1.74 v (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) package drawings, thermal data, and symbolization are available at www.ti.com/packaging . (3) voltage is fixed and not programmable. table 3. default device options part number (1) (2) buck1 buck2 ldo1 ldo2 buck modes default en_t delay default uvlo lp3907sq-pxpp/nopb 1.5 v 3.3 v 2.5 v 2.5 v auto-mode 010 enabled lp3907sqx-pxpp/nopb 1.5 v 3.3 v 2.5 v 2.5 v auto-mode 010 enabled lp3907sq-tjxip/nopb 1.2 v 3.3 v 1.8 v 2.5 v forced pwm 001 enabled lp3907sqx-tjxip/nopb 1.2 v 3.3 v 1.8 v 2.5 v forced pwm 001 enabled lp3907sq-jxqx/nopb 1.2 v 3.3 v 2.6 v 3.3 v auto-mode 010 enabled lp3907sqx-jxqx/nopb 1.2 v 3.3 v 2.6 v 3.3 v auto-mode 010 enabled lp3907sq-jyqx/nopb 1.2 v 3.4 v 2.6 v 3.3 v auto-mode 010 enabled lp3907sqx-jyqx/nopb 1.2 v 3.4 v 2.6 v 3.3 v auto-mode 010 enabled lp3907sq-pjxix/nopb 1.2 v 3.3 v 1.8 v 3.3 v forced pwm 010 enabled lp3907sqx-pjxix/nopb 1.2 v 3.3 v 1.8 v 3.3 v forced pwm 010 enabled lp3907sq-pfx6w/nopb 1 v 3.3 v 2.65 v (3) 3.2 v forced pwm 010 enabled lp3907sqx-pfx6w/nopb 1 v 3.3 v 2.65 v (3) 3.2v forced pwm 010 enabled lp3907sq-bjx6x/nopb 1.2 v 3.3 v 2.65 v (3) 3.3 v forced pwm 010 disabled lp3907sqx-bjx6x/nopb 1.2v 3.3 v 2.65 v (3) 3.3 v forced pwm 010 disabled lp3907sq-bjxqx/nopb 1.2 v 3.3 v 2.6 v 3.3 v forced pwm 010 disabled lp3907sqx-bjxqx/nopb 1.2 v 3.3 v 2.6 v 3.3 v forced pwm 010 disabled lp3907sq-bjyqx/nopb 1.2 v 3.4 v 2.6 v 3.3 v forced pwm 010 disabled lp3907sqx-bjyqx/nopb 1.2 v 3.4 v 2.6 v 3.3 v forced pwm 010 disabled lp3907sq-bjxix/nopb 1.2 v 3.3 v 1.8 v 3.3 v forced pwm 010 disabled lp3907sqx-bjxix/nopb 1.2 v 3.3 v 1.8 v 3.3 v forced pwm 010 disabled lp3907sq-bfx6w/nopb 1 v 3.3 v 2.65 v (3) 3.2 v forced pwm 010 disabled lp3907sqx-bfx6w/nopb 1 v 3.3 v 2.65 v (3) 3.2 v forced pwm 010 disabled lp3907sq-vrzx/nopb 1.8 v 2.7 v 3.5 v 3.3 v auto-mode 010 enabled lp3907sqx-vrzx/nopb 1.8 v 2.7 v 3.5 v 3.3 v auto-mode 010 enabled lp3907tl-jj11/nopb 1.2 v 1.8 v 2.85 v (3) 2.85 v (3) auto-mode 010 enabled lp3907tlx-jj11/nopb 1.2 v 1.8 v 2.85 v (3) 2.85 v (3) auto-mode 010 enabled lp3907tl-jsxs/nopb 1.2 v 2.8 v 3.3 v 2.8 v auto-mode 010 enabled lp3907tlx-jsxs/nopb 1.2 v 2.8 v 3.3 v 2.8 v auto-mode 010 enabled
4 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated table 3. default device options (continued) part number (1) (2) buck1 buck2 ldo1 ldo2 buck modes default en_t delay default uvlo lp3907tl-jjcp/nopb 1.2 v 1.8 v 1.2 v 2.5 v auto-mode 010 enabled lp3907tlx-jjcp/nopb 1.2 v 1.8 v 1.2 v 2.5 v auto-mode 010 enabled lp3907tl-plnto/nopb 1.3 v 2.2 v 2.9 v 2.4 v forced pwm 010 enabled lp3907tlx-plnto/nopb 1.3 v 2.2 v 2.9 v 2.4 v forced pwm 010 enabled 6 pin configuration and functions rtw package 24-pin wqfn top view yzr package 25-pin dsbga top view a b c d e sw1 vin ldo12 gnd_c scl 54 3 2 1 vin1 vin ldo2 ldo2 avdd fb2 ldo1 gnd_s w1 fb1 en_s w1 en_t vin ldo12 npor en_ ldo1 sda vin2 sw2 gnd_ sw2 vin ldo1 en_ ldo2 en_ sw2 gnd_ l 7 8 9 10 11 12 21 20 19 24 23 22 1 2 3 4 5 6 13 14 18 17 16 15
5 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) a: analog pin d: digital pin g: ground pin pwr: power pin i: input pin i/o: input/output pin o: output pin. pin functions pin i/o type (1) description wqfn numbe r dsbga number name 1 b4, b5 vinldo12 i pwr analog power for internal functions (vref, bias, i 2 c, logic) 2 c4 en_t i d enable for preset power on sequence. (see .) 3 c3 npor o d npor power on reset pin for both buck1 and buck 2. open drain logic output 100-k pullup resistor. npor is pulled to ground when the voltages on these supplies are not good. see flexible power-on reset (power good with delay) section for more info. 4 c5 gnd_sw1 g g buck1 nmos power ground 5 d5 sw1 o pwr buck1 switcher output pin 6 e5 vin1 i pwr power in from either dc source or battery to buck1 7 d4 ensw1 i d enable pin for buck1 switcher, a logic high enables buck1 8 e4 fb1 i a buck1 input feedback terminal 9 d3 gnd_c g g non switching core ground pin 10 e3 avdd i pwr analog power for buck converters 11 e2 fb2 i a buck2 input feedback terminal 12 d2 ensw2 i d enable pin for buck2 switcher, a logic high enables buck2 13 e1 vin2 i pwr power in from either dc source or battery to buck2 14 d1 sw2 o pwr buck2 switcher output pin 15 c1 gnd_sw2 g g buck2 nmos power ground 16 c2 sda i/o d i 2 c cata (bidirectional) 17 b2 scl i d i 2 c clock 18 b1 gnd_l g g ldo ground 19 a1 vinldo1 i pwr power in from either dc source or battery to input terminal to ldo1 20 a2 ldo1 o pwr ldo1 output 21 b3 enldo1 i d ldo1 enable pin, a logic high enables the ldo1 22 a3 enldo2 i d ldo2 enable pin, a logic high enables the ldo2 23 a4 ldo2 o pwr ldo2 output 24 a5 vinldo2 i pwr power in from either dc source or battery to input terminal to ldo2. dap dap gnd gnd connection is not necessary for electrical performance, but it is recommended for better thermal dissipation.
6 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions (bucks) . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to the potential at the gnd pin. (3) in applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. maximum ambient temperature (t a-max ) is dependent on the maximum operating junction temperature (t j-max-op = 125 c), the maximum power dissipation of the device in the application (p d-max ), and the junction-to-ambient thermal resistance of the part/package in the application (r ja ), as given by the following equation: t a-max = t j-max-op ? (r ja p d-max ). 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit v in , sda, scl ? 0.3 6 v gnd to gnd slug 0.3 v power dissipation (wqfn (rtw)) (p d_max ) (t a = 85 c, t max = 125 c ) (3) 1.43 w power dissipation (dsbga (yzr)) (3) (p d_max ) (t a = 85 c, t max = 125 c ) 0.78 w junction temperature, t j-max 150 c maximum lead temperature (soldering) 260 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 750 (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to the potential at the gnd pin. (3) minimum (minimum) and maximum (maximum) limits are ensured by design, test, or statistical analysis. typical numbers are not ensured, but do represent the most likely norm. (4) buck v in v out + 1 v. (5) junction-to-ambient thermal resistance is highly application and board-layout dependent. in applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. 7.3 recommended operating conditions (bucks) over operating free-air temperature range (unless otherwise noted) (1) (2) (3) (4) min max unit v in 2.8 5.5 v v en 0 (v in + 0.3 v) v junction temperature, t j ? 40 125 c ambient temperature, t a (5) ? 40 85 c
7 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) junction-to-ambient thermal resistance is highly application and board-layout dependent. in applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. (2) internal thermal shutdown circuitry protects the device from permanent damage. thermal shutdown engages at t j = 160 c (typical) and disengages at t j = 140 c (typical) (3) in applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. maximum ambient temperature (t a-max ) is dependent on the maximum operating junction temperature (t j-max-op = 125 c), the maximum power dissipation of the device in the application (p d-max ), and the junction-to-ambient thermal resistance of the part/package in the application (r ja ), as given by the following equation: t a-max = t j-max-op ? (r ja p d-max ). (4) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 7.4 thermal information see (1) (2) (3) thermal metric (4) lp3907 unit rtw yzr 24 pins 25 pins r ja junction-to-ambient thermal resistance 32.7 58.7 c/w r jc(top) junction-to-case (top) thermal resistance 31.2 0.3 c/w r jb junction-to-board thermal resistance 11.2 8.0 c/w jt junction-to-top characterization parameter 0.2 0.6 c/w jb junction-to-board characterization parameter 11.2 8.0 c/w r jc(bot) junction-to-case (bottom) thermal resistance 1.4 n/a c/w (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to the potential at the gnd pin. (3) this specification is ensured by design. (4) vpor is voltage at which the eprom resets. this is different from the uvlo on vinldo12, which is the voltage at which the regulators shut off, and is also different from the npor function, which signals if the regulators are in a specified range. 7.5 general electrical characteristics unless otherwise noted, v in = 3.6 v and t j = 25 c. (1) (2) (3) (4) parameter test conditions min typ max unit i q vinldo12 shutdown current v in = 3.6 v 3 a v por power-on reset threshold v dd falling edge (4) 1.9 v t sd thermal shutdown threshold 160 c t sdh thermal shutdown hysteresis 20 c uvlo undervoltage lockout rising 2.9 v falling 2.7
8 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) all voltages are with respect to the potential at the gnd pin. (2) minimum (min) and maximum (max) limits are ensured by design, test, or statistical analysis. typical numbers are not ensured, but do represent the most likely norm. (3) c in , c out : low-esr surface-mount ceramic capacitors (mlccs) used in setting electrical characteristics. (4) the device maintains a stable, regulated output voltage without a load. (5) dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mv below its nominal value. (6) quiescent current is defined here as the difference in current between the input voltage source and the load at v out . (7) v in minimum for line regulation values is 1.8 v. (8) pins 24, 19 can operate from v in min of 1.74 v to a v in max of 5.5 v. this rating is only for the series pass pmos power fet. it allows the system design to use a lower voltage rating if the input voltage comes from a buck output. (9) limits apply over the entire junction temperature range for operation, ? 40 c to +125 c. (10) the i q can be defined as the standing current of the lp3907 when the i 2 c bus is active and all other power blocks have been disabled via the i 2 c bus, or it can be defined as the i 2 c bus active, and the other power blocks are active under no load condition. these two values can be used by the system designer when the lp3907 is powered using a battery. (11) the i q exhibits a higher current draw when the en pin is de-asserted because the i 2 c buffer pins draw an additional 2 a. 7.6 low dropout regulators, ldo1 and ldo2 unless otherwise noted, v in = 3.6 v, c in = 1 f, c out = 0.47 f, and t j = 25 c. (1) (2) (3) (4) (5) (6) (7) parameter test conditions min typ max unit v in operational voltage range vinldo1 and vinldo2 pmos pins (8) 1.74 (9) 5.5 (9) v v out accuracy output voltage accuracy (default v out ) load current = 1 ma ? 3% (9) 3% (9) v out line regulation v in = (v out + 0.3 v) to 5 v, (7) , load current = 1 ma 0.15 (9) %/v load regulation v in = 3.6 v, load current = 1 ma to i max 0.011 (9) %/ma i sc short circuit current limit ldo1-2, v out = 0 v 500 ma v in ? v out dropout voltage load current = 50 ma (5) 30 200 (9) mv psrr power supply ripple rejection ? = 10 khz, load current = i max 45 db e n supply output noise 10 hz < f < 100 khz 80 vrms i q (6) (10) quiescent current on i out = 0 ma 40 a quiescent current on i out = i max 60 a quiescent current off en is de-asserted (11) 0.03 a t on turnon time start-up from shutdown 300 s c out output capacitor capacitance for stability 0 c t j 125 c 0.33 (9) 0.47 f ? 40 c t j 125 c 0.68 1 f esr 5 (9) 500 (9) m ? (1) all voltages are with respect to the potential at the gnd pin. (2) minimum (min) and maximum (max) limits are ensured by design, test, or statistical analysis. typical numbers are not ensured, but do represent the most likely norm. (3) c in , c out : low-esr surface-mount ceramic capacitors (mlccs) used in setting electrical characteristics. (4) the device maintains a stable, regulated output voltage without a load. (5) quiescent current is defined here as the difference in current between the input voltage source and the load at v out . (6) buck v in v out + 1 v. (7) limits apply over the entire junction temperature range for operation, ? 40 c to +125 c. 7.7 buck converters sw1, sw2 unless otherwise noted, v in = 3.6 v, c in = 10 f, c out = 10 f, l out = 2.2- h ceramic, and t j = 25 c. (1) (2) (3) (4) (5) (6) parameter test conditions min typ max unit v fb feedback voltage ? 3% (7) 3% (7) v out line regulation 2.8 v < v in < 5.5 v i out = 10 ma 0.089 %/v load regulation 100 ma < i out < i max 0.0013 %/ma eff efficiency load current = 250 ma 96% i shdn shutdown supply current en is de-asserted 0.01 a ? osc internal oscillator frequency 1.7 (7) 2.1 mhz
9 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated buck converters sw1, sw2 (continued) unless otherwise noted, v in = 3.6 v, c in = 10 f, c out = 10 f, l out = 2.2- h ceramic, and t j = 25 c. (1) (2) (3) (4) (5) (6) parameter test conditions min typ max unit (8) the i q can be defined as the standing current of the lp3907 when the i 2 c bus is active and all other power blocks have been disabled via the i 2 c bus, or it can be defined as the i 2 c bus active, and the other power blocks are active under no load condition. these two values can be used by the system designer when the device is powered using a battery. i peak buck1 peak switching current limit 1.5 a buck2 peak switching current limit 1 i q (8) quiescent current ? on ? no load pfm mode 33 a r dson (p) pin-pin resistance pfet 200 m ? r dson (n) pin-pin resistance nfet 180 m ? t on turnon time start up from shutdown 500 s c in input capacitor capacitance for stability 10 f c out output capacitor capacitance for stability 10 f (1) this specification is ensured by design. 7.8 i/o electrical characteristics unless otherwise noted: limits apply over the entire junction temperature range for operation, t j = ? 40 c to +125 c. (1) parameter test conditions min max unit v il input low level 0.4 v v ih input high level 1.2 7.9 power-on reset (por) threshold/function parameter test conditions min typ max unit npor npor = power on reset forbuck1 and buck2 default 50 ms npor threshold percentage of target voltage buck1 or buck2 v buck1 and v buck2 rising 94% v buck1 or v buck2 falling 85% vol output level low load = iol = 500 ma 0.23 0.5 v (1) this specification is ensured by design. 7.10 i 2 c interface timing requirements unless otherwise noted, v in = 3.6 v and t j = 25 c. (1) min nom max unit ? clk clock frequency 400 khz t bf bus-free time between start and stop see (1) 1.3 s t hold hold time repeated start condition 0.6 s t clklp clk low period 1.3 s t clkhp clk high period 0.6 s t su set-up time repeated start condition 0.6 s t datahld data hold time 0 s t datasu data set-up time 100 ns t su set-up time for start condition 0.6 s t trans maximum pulse width of spikes that must be suppressed by the input filter of both data & clk signals 50 ns
10 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 7.11 typical characteristics ? ldo t a = 25 c unless otherwise noted. v in = 3.6 v v out = 2.6 v 100-ma load figure 1. output voltage change vs temperature (ldo1) v in = 3.6 v v out = 2.6 v 100-ma load figure 2. output voltage change vs temperature (ldo2) v in = 3.6 v v out = 2.6 v 0 to 150-ma load figure 3. load transient (ldo1) v in = 3.6 v v out = 3.3 v 0 to 150-ma load figure 4. load transient (ldo2) v in = 3.6 to 4.2 v v out = 2.6 v 300-ma load figure 5. line transient (ldo1) v in = 3.6 to 4.2 v v out = 3.3 v 300-ma load figure 6. line transient (ldo2) temperature (c) v out change (%) 2.00 1.50 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00 -50 -35 -20 -5 10 25 40 55 70 85 100 temperature (c) v out change (%) 2.00 1.50 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00 -50 -35 -20 -5 10 25 40 55 70 85 100
11 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated typical characteristics ? ldo (continued) t a = 25 c unless otherwise noted. v in = 0 to 3.6 v v out = 2.6 v 1-ma load figure 7. enable start-up time (ldo1) v in = 0 to 3.6 v v out = 3.3 v 1-ma load figure 8. enable start-up time (ldo2) v in = 1.74 v figure 9. ldo maximum load v out ( )v maximum load (ma) 300 250 200 150 100 1.00 1.10 1.20 1.30 1.40 1.50 1.60 vin = 1.74v
12 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 7.12 typical characteristics ? bucks v in = 2.8 v to 5.5 v, t a = 25 c figure 10. shutdown current vs. temp v out = 1 v figure 11. output voltage vs. supply voltage v out = 1.8 v figure 12. output voltage vs. supply voltage v out = 3.5 v figure 13. output voltage vs. supply voltage supply voltage (v) v out (v) 1.85 1.83 1.81 1.79 1.77 1.75 2.7 3.3 3.8 4.4 4.9 i out = 20 ma i out = 750 ma i out = 1.0a supply voltage (v) v out (v) 3.35 3.33 3.31 3.29 3.27 3.25 4.0 4.5 5.0 5.5 i out = 20 ma i out = 300 ma i out = 600 ma temperature (c) shutdown current ( a) 0.15 0.12 0.09 0.06 0.03 0.00 -40 -20 0 20 40 60 80 vin = 2.7v vin = 3.6v vin = 5.5v supply voltage (v) v out (v) 1.05 1.03 1.01 0.99 0.97 0.95 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i out = 20 ma i out = 750 ma i out = 1.0a
13 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 7.13 typical characteristics ? buck1 v in = 2.8 v to 5.5 v, t a = 25 c, v out = 1.2 v, 2 v v out = 1.2 v l= 2.2 h figure 14. efficiency vs output current (forced pwm mode) v out = 2v l= 2.2 h figure 15. efficiency vs output current (forced pwm mode) v out = 1.2 v l= 2.2 h figure 16. efficiency vs output current (pwm-to-pfm mode) v out = 2 v l= 2.2 h figure 17. efficiency vs output current (pwm-to-pfm mode) output current (ma) efficiency (%) 100 90 80 70 60 50 40 0.1 1 10 100 1000 v in = 2.8v v in = 3.6v v in = 5.5v output current (ma) efficiency (%) 100 9080 70 60 50 40 0.1 1 10 100 1000 v = 2.8v in v = 3.6v in v = 5.5v in output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0.1 1 10 100 1000 v in = 2.8v v in = 3.6v v in = 5.5v output current (ma) efficiency (%) 0.1 1 10 100 1000 v = 2.8v in v = 3.6v in v = 5.5v in 100 9080 70 60 50 40 30 20 10
14 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 7.14 typical characteristics ? buck2 v in = 4.5 v to 5.5 v, t a = 25 c, v out = 1.8 v, 3.3 v v out = 1.8 v l= 2.2 h figure 18. efficiency vs output current (forced pwm mode) v out = 3.3 v l= 2.2 h figure 19. efficiency vs output current (forced pwm mode) v out = 1.2 v l= 2.2 h figure 20. efficiency vs output current (pwm-to-pfm mode) v out = 2 v l= 2.2 h figure 21. efficiency vs output current (pwm-to-pfm mode) output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0.1 1 10 100 1000 v = 4.5v in v = 5.5v in output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0.1 1 10 100 1000 v = 4.5v in v = 5.5v in output current (ma) efficiency (%) 100 90 80 70 60 50 40 0.1 1 10 100 1000 v = 4.5v in v = 5.5v in output current (ma) efficiency (%) 100 90 80 70 60 50 40 0.1 1 10 100 1000 v = 4.5v in v = 5.5v in
15 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 7.15 typical characteristics ? bucks v in = 3.6 v, t a = 25 c, v out = 1.2 v unless otherwise noted. v out = 1.2 v i load = 300 to 500 ma figure 22. load transient response (pwm mode) v out = 1.2 v i load = 50 to 150 ma figure 23. mode change by load transient (pfm-to-pwm mode) v in = 3.6 to 4.2 v v out = 1.2 v 250-ma load figure 24. line transient response v in = 3.6 to 4.2 v v out = 3.3 v 250-ma load figure 25. line transient response v out = 1.2 v 1-a load figure 26. start-up into pwm mode v out = 3.3 v 600-ma load figure 27. start-up into pwm mode
16 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated typical characteristics ? bucks (continued) v in = 3.6 v, t a = 25 c, v out = 1.2 v unless otherwise noted. v out = 1.2 v 30-ma load figure 28. start-up into pfm mode v out = 3.3 v 30-ma load figure 29. start-up into pfm mode
17 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) for default values of the regulators, consult table 3 . 8 detailed description 8.1 overview the lp3907 supplies the various power needs of the application by means of two linear low drop regulators (ldo1 and ldo2) and two buck converters (sw1 and sw2). table 4 lists the output characteristics of the various regulators. table 4. supply specification supply (1) load output v out range (v) resolution (mv) i max maximum output current (ma) ldo1 analog 1 to 3.5 100 300 ldo2 analog 1 to 3.5 100 300 sw1 digital 0.8 to 2 50 1000 sw2 digital 1 to 3.5 100 600 8.2 functional block diagram osc logic control and registers i 2 c sw2 vfb2 cvdd 4.7 p f npor buck1 buck2 lsw1 sw1 vfb1 ldo2 reset ldo2 gnd_c bias thermal shutdown power on reset lsw1 vinldo 1 avdd vbuck2 ldo1 ldo1 cldo1 vinldo12 cldo2 power on-off logic vbuck1 en_t enldo1 enldo2 ensw 1 ensw 2 vinldo2 avdd avdd 1 uf + vdd rdy1 rdy2 ulvo vin ok 100k 10 p f 1 p f 1 p f 1 p f li-ion/polymer cell 3.3v - 4.2v dc source 4.5v - 5.5v gnd_l gnd_sw2 gnd_sw1 i 2 c_sda i 2 c_scl 1.8v 0.47 p f 0.47 p f 3.3v 10 p f 3.3v 10 p f 1.2v 2.2 p h 2.2 p h 10 p f vinldo12 vinldo2 vinldo1 vin1 vin2 copyright ? 2016, texas instruments incorporated
18 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.3 feature description 8.3.1 dc-dc converters 8.3.1.1 linear low dropout regulators (ldos) ldo1 and ldo2 are identical linear regulators targeting analog loads characterized by low noise requirements. ldo1 and ldo2 are enabled through the enldo pin or through the corresponding ldo1 or ldo2 control register. the output voltages of both ldos are register programmable. the default output voltages are factory programmed during final test, which can be tailored to the specific needs of the system designer. figure 30. ldo block diagram 8.3.1.2 no-load stability the ldos remain stable and in regulation with no external load. this is an important consideration in some circuits, for example, cmos ram keep-alive applications. 8.3.1.3 ldo and ldo2 control registers ldo1 and ldo2 can be configured by means of the ldo1 and ldo2 control registers. the output voltage is programmable in steps of 100 mv from 1 v to 3.5 v by programming bits d4-d0 in the ldo control registers. both ldo1 and ldo2 are enabled by applying a logic 1 to the enldo1 and enldo2 pin. enable/disable control is also provided through enable bit of the ldo1 and ldo2 control registers. the value of the enable ldo bit in the register is logic 1 by default. the output voltage can be altered while the ldo is enabled. 8.3.2 sw1, sw2: synchronous step-down magnetic dc-dc converters 8.3.2.1 functional description the lp3907 incorporates two high-efficiency synchronous switching buck regulators, sw1 and sw2, that deliver a constant voltage from a single li-ion battery to the portable system processors. using a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 1000 ma and 600 ma, respectively, depending on the input voltage and output voltage (voltage headroom), and the inductor chosen (maximum current capability). there are three modes of operation depending on the current required: pwm, pfm, and shutdown. pwm mode handles current loads of approximately 70 ma or higher, delivering voltage precision of 3% with 90% efficiency or better. lighter output current loads cause the device to automatically switch into pfm for reduced current consumption (i q = 15 a typical) and a longer battery life. the standby operating mode turns off the device, offering the lowest current consumption. pwm or pfm mode is selected automatically or pwm mode can be forced through the setting of the buck control register. both sw1 and sw2 can operate up to a 100% duty cycle (pmos switch always on) for low drop out control of the output voltage. in this way the output voltage is controlled down to the lowest possible input voltage. additional features include soft-start, undervoltage lockout, current overload protection, and thermal overload protection. vin enldo vldo gnd + - vref ldo register controlled copyright ? 2016, texas instruments incorporated
19 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated feature description (continued) 8.3.2.2 circuit operation description a buck converter contains a control block, a switching pfet connected between input and output, a synchronous rectifying nfet connected between the output and ground (bckgnd pin) and a feedback path. during the first portion of each switching cycle, the control block turns on the internal pfet switch. this allows current to flow from the input through the inductor to the output filter capacitor and load. the inductor limits the current to a ramp with a slope of (1) by storing energy in a magnetic field. during the second portion of each cycle, the control block turns the pfet switch off, blocking current flow from the input, and then turns the nfet synchronous rectifier on. the inductor draws current from ground through the nfet to the output filter capacitor and load, which ramps the inductor current down with a slope of (2) the output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. 8.3.2.3 pwm operation during pwm operation the converter operates as a voltage-mode controller with input voltage feed forward. this allows the converter to achieve excellent load and line regulation. the dc gain of the power stage is proportional to the input voltage. to eliminate this dependence, feed forward voltage inversely proportional to the input voltage is introduced. 8.3.2.4 internal synchronous rectification while in pwm mode, the buck uses an internal nfet as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. 8.3.2.5 current limiting a current limit feature allows the converter to protect itself and external components during overload conditions. pwm mode implements current limiting using an internal comparator that trips at 1.5 a for buck1 and at 1 a for buck2 (typical). if the output is shorted to ground the device enters a timed current limit mode where the nfet is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. 8.3.2.6 pfm operation at very light loads, the converter enters pfm mode and operates with reduced switching frequency and supply current to maintain high efficiency. the part automatically transitions into pfm mode when either of two conditions occurs for a duration of 32 or more clock cycles: 1. the inductor current becomes discontinuous, or 2. the peak pmos switch current drops below the i mode level (3) v in 160 : i mode < 66 ma ) (typically + -v out l v in - v out l
20 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated feature description (continued) during pfm operation, the converter positions the output voltage slightly higher than the nominal output voltage during pwm operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. the pfm comparators sense the output voltage via the feedback pin and control the switching of the output fets such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal pwm output voltage. if the output voltage is below the low pfm comparator threshold, the pmos power switch is turned on. it remains on until the output voltage exceeds the ? high ? pfm threshold or the peak current exceeds the i pfm level set for pfm mode. the typical peak current in pfm mode is: (4) once the pmos power switch is turned off, the nmos power switch is turned on until the inductor current ramps to zero. when the nmos zero-current condition is detected, the nmos power switch is turned off. if the output voltage is below the high pfm comparator threshold (see figure 31 ), the pmos switch is again turned on and the cycle is repeated until the output reaches the desired level. once the output reaches the high pfm threshold, the nmos switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. quiescent supply current during this sleep mode is less than 30 a, which allows the part to achieve high efficiencies under extremely light load conditions. when the output drops below the low pfm threshold, the cycle repeats to restore the output voltage to approximately 1.6% above the nominal pwm output voltage. if the load current increases during pfm mode (see figure 31 ) causing the output voltage to fall below the ? low2 ? pfm threshold, the part automatically transitions into fixed-frequency pwm mode. 8.3.2.7 sw1, sw2 operation sw1 and sw2 have selectable output voltages ranging from 0.8 v to 3.5 v (typical). both sw1 and sw2 in the lp3907 are i 2 c register controlled and are enabled by default through the internal state machine of the device following a power-on event that moves the operating mode to the active state. (see flexible power sequencing of multiple power supplies .) the sw1 and sw2 output voltages revert to default values when the power-on sequence has been completed. the default output voltage for each buck converter is factory programmable. (see application and implementation .) 8.3.2.8 sw1, sw2 control registers sw1, sw2 can be enabled/disabled through the corresponding control register. the modulation mode pwm/pfm is by default automatic and depends on the load as described above in the functional description. the modulation mode can be overridden by setting i 2 c bit to a logic 1 in the corresponding buck control register, forcing the buck to operate in pwm mode regardless of the load condition. figure 31. operation in pfm mode and transfer to pwm mode high pfm threshold ~1.016 * vout low1 pfm threshold ~1.008 * vout pfm mode at light load pwm mode at moderate to heavy loads pfet on until ipfm limit reached nfet on drains inductor current until i inductor = 0 high pfm voltage threshold reached, go into sleep mode low pfm threshold, turn on pfet current load increases, draws vout towards low2 pfm threshold low2 pfm threshold, switch back to pwmmode load current increases low2 pfm threshold vout z- a xi s z - axis v in 80 : i pfm = 66 ma +
21 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated feature description (continued) 8.3.2.9 soft start the soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. the two lp3907 buck converters have a soft-start circuit that limits in- rush current during start-up. during start-up the switch current limit is increased in steps. soft start is activated only if en goes from logic low to logic high after v in reaches 2.8v. soft start is implemented by increasing switch current limit in steps of 180 ma, 300 ma, and 720 ma for buck1; 161 ma, 300 ma, and 536 ma for buck2 (typical switch current limit). the start-up time thereby depends on the output capacitor and load current demanded at start-up. 8.3.2.10 low dropout operation the lp3907 can operate at 100% duty cycle (no switching; pmos switch completely on) for low dropout support of the output voltage. in this way the output voltage is controlled down to the lowest possible input voltage. when the device operates near 100% duty cycle, output voltage ripple is approximately 25 mv. the minimum input voltage needed to support the output voltage is: v in, min = i load (r dson, pfet + r inductor ) + v out where ? i load = load current ? r dson, pfet = drain to source resistance of pfet switch in the triode region ? r inductor = inductor resistance (5) 8.3.2.11 flexible power sequencing of multiple power supplies the lp3907 provides several options for power on sequencing. the two bucks can be individually controlled with ensw1 and ensw2. the two ldos can also be individually controlled with enldo1 and enldo2. if the user desires a set power on sequence, the chip is programmable through i 2 c and raise en_t from low to high to activate the power on sequencing. 8.3.2.12 power-up sequencing using the en_t function en_t assertion causes the lp3907 to emerge from standby mode to full operation mode at a preset timing sequence. by default, the enables for the ldos and bucks (enldo1, enldo2, en_t, ensw1, ensw2) are 500 k internally pulled down, which causes the part to stay off until enabled. if the user wishes to use the preset timing sequence to power on the regulators, transition the en_t pin from low to high. otherwise, simply tie the enables of each specific regulator high to turn on automatically. en_t is edge triggered with rising edge signaling the chip to power on. the en_t input is deglitched, and the default is set at 1 ms. as shown in figure 32 and figure 33 , a rising en_t edge starts a power-on sequence, while a falling en_t edge starts a shutdown sequence. if en_t is high, toggling the external enables of the regulators has no effect on the chip. the regulators can also be programmed through i 2 c to turn on and off. by default, i 2 c enables for the regulators turned on. the regulators are on following the pattern below: regulators on = (i 2 c enable) and (external pin enable or en_t high). note the en_t power-up sequencing may also be employed immediately after v in is applied to the device. however, v in must be stable for approximately 8 ms minimum before en_t be asserted high to ensure internal bias, reference, and the flexible por timing are stabilized. this initial en_t delay is necessary only upon first time device power on for power sequencing function to operate properly. if the device is powered, the en_t logic must be stable for 12 ms minimum before switching state.
22 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated feature description (continued) figure 32. power rail enable logic figure 33. lp3907 default power-up sequence table 5. power-on timing specification description min nom typ unit t 1 programmable delay from en_t assertion to v cc _buck1 on 1.5 ms t 2 programmable delay from en_t assertion to v cc _buck2 on 2 ms t 3 programmable delay from en_t assertion to v cc _ldo1 on 3 ms t 4 programmable delay from en_t assertion to v cc _ldo2 on 6 ms figure 34. lp3907 default power-off sequence i 2 c ext_enable pins regulator on start programmed timing sequence 0 1 en_t en_t vout buck1 vout buck2 vout ldo1 vout ldo2 t 1 t 2 t 3 t 4 en_t vout buck1 vout buck2 vout ldo1 vout ldo2 t 2 t 3 t 4 t 1
23 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated table 6. power-off timing specification description min nom max unit t 1 programmable delay from en_t deassertion to v cc _buck1 off 1.5 ms t 2 programmable delay from en_t deassertion to v cc _buck2 off 2 ms t 3 programmable delay from en_t deassertion to v cc _ldo1 off 3 ms t 4 programmable delay from en_t deassertion to v cc _ldo2 off 6 ms 8.3.3 flexible power-on reset (power good with delay) the lp3907 is equipped with an internal power-on-reset (por) circuit which monitors the output voltage levels on bucks 1 and 2. the npor is an open drain logic output which is logic low when either of the buck outputs are below 91% of the rising value, or when one or both outputs fall below 82% of the desired value. the time delay between output voltage level and npor is enabled is (50 s, 50 ms, 100 ms, 200 ms) 50 ms by default. the system designer can choose the external pullup resistor (that is, 100 k ? ) for the npor pin. figure 35. npor with counter delay en1 npor rdy1 en2 rdy2 en1 npor rdy1 en2 rdy2 0v 0v case1 case2 en1 npor rdy1 en2 rdy2 case3 counter delay t1 t2 t1 t2 counter delay t1 t2 counter delay
24 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated figure 35 shows the simplest application of the por, where both switcher enables are tied together. in case 1, en1 causes npor to transition low and triggers the npor delay counter. if the power supply for buck2 does not come on within that period, npor stays low, indicating a power fail mode. case 2 indicates the vice versa scenario if buck1 supply did not come on. in both cases the npor remains low. case 3 shows a typical application of the por, where both switcher enables are tied together. even if rdy1 ramps up slightly faster than rdy2 (or vice versa), then npor signal triggers a programmable delay before going high, as explained below. figure 36. faults occurring in counter delay after start-up figure 36 details the power good with delay with respect to the enable signals en1, and en2. the rdy1, rdy2 are internal signals derived from the output of two comparators. each comparator has been trimmed as follows: comparator level buck supply level high greater than 94% low less than 85% the circuits for en1 and rdy1 is symmetrical to en2 and rdy2, so each reference to en1 and rdy1 also works for en2 and rdy2 and vice versa. if en1 and rdy1 signals are high at time t1, then the rdy1 signal rising edge triggers the programmable delay counter (50 s, 50 ms, 100 ms, 200 ms). this delay forces npor low between time interval t1 and t2. npor is then pulled high after the programmable delay is completed. now if en2 and rdy2 are initiated during this interval the npor signal ignores this event. if either rdy1or rdy2 were to go low at t3 then the programmable delay is triggered again. en1 npor rdy1 t1 t2 t3 t4 t0 en2 rdy2 counter delay counter delay
25 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated figure 37. npor mask window if the en1 and rdy1 are initiated in normal operation, then npor is asserted and deasserted as explained in figure 37 . case 1 shows the case where en2 and rdy2 are initiated after triggered programmable delay. to prevent the npor being asserted again, a masked window (5 ms) counter delay is triggered off the en2 rising edge. npor is still held high for the duration of the mask, whereupon the npor status afterwards depends on the status of both rdy1 and rdy2 lines. case 2 shows the case where en2 is initiated after the rdy1 triggered programmable delay, but rdy2 never goes high (buck2 never turns on). normal operation operation of npor occurs wilth respect to en1 and rdy1, and the npor signal is held high for the duration of the mask window. we see that npor goes low after the masking window has timed out because it is now dependent on rdy1 and rdy2, where rdy2 is low. rdy1 t1 t2 t3 t4 t0 rdy2 counter delay en1 en2 npor counter delay npor mask time counter delay 0v case 2: case 1: mask window mask window rdy2 en2 npor mask time
26 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated figure 38. design implementation of the flexible power-on reset an internal power-on reset of the device is used with en1, and en2 to produce a reset signal (low) to the delay timer npor. en1 and rdy1 or en2 and rdy2 are used to generate the set signal (high) to the delay timer. s = r = 1 never occurs. the mask timers are triggered off en1 and en2 which are gated with rdy1, and rdy2 to generate outputs to the final and gate to generate the npor. 8.3.4 undervoltage lockout the lp3907 features an undervoltage lockout circuit. the function of this circuit is to continuously monitor the raw input supply voltage (vinldo12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 vdc. the circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 vdc trip point for a v in ok ? not ok detector. this v in ok signal is then used to gate the enable signals to the four regulators of the device. when vinldo12 is greater than 2.8 vdc the four enables control the four regulators, when vinldo12 is less than 2.8 vdc the four regulators are disabled by the v in detector being in the ? not ok ? state. the circuit has built-in hysteresis to prevent chattering occurring. 8.4 device functional modes 8.4.1 shutdown mode during shutdown the pfet switch, reference, control and bias circuitry of the converters are turned off. the nfet switch is on in shutdown to discharge the output. when the converter is enabled, soft start is activated. it is recommended to disable the converter during the system power up and undervoltage conditions when the supply is less than 2.8 v. delay mask counter delay mask counter q q r s delay npor en1 rdy1 en2 rdy2 por
27 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.5 programming 8.5.1 i 2 c-compatible serial interface 8.5.1.1 i 2 c signals the lp3907features an i 2 c-compatible serial interface, using two dedicated pins: scl and sda for i 2 c clock and data respectively. both signals need a pullup resistor according to the i 2 c specification. the lp3907 interface is an i 2 c slave that is clocked by the incoming scl clock. signal timing specifications are according to the i 2 c bus specification. the maximum bit rate is 400kbit/s. see i 2 c specification from nxp semiconductors for further details. 8.5.1.2 i 2 c data validity the data on the sda line must be stable during the high period of the clock signal (scl); for example, the state of the data line can only be changed when clk is low. figure 39. i 2 c signals: data validity 8.5.1.3 i 2 c start and stop conditions start and stop bits classify the beginning and the end of the i 2 c session. start condition is defined as the sda signal transitioning from high to low while the scl line is high. stop condition is defined as the sda transitioning from low to high while the scl is high. the 2 c master always generates start and stop bits. the i 2 c bus is considered to be busy after start condition and free after stop condition. during data transmission, i 2 c master can generate repeated start conditions. first start and repeated start conditions are equivalent, function-wise. figure 40. start and stop conditions 8.5.1.4 transferring data every byte put on the sda line must be eight bits long, with the most significant bit (msb) being transferred first. each byte of data has to be followed by an acknowledge bit. the acknowledged related clock pulse is generated by the master. the transmitter releases the sda line (high) during the acknowledge clock pulse. the receiver must pull down the sda line during the 9th clock pulse, signifying acknowledgment. a receiver which has been addressed must generate an acknowledgment ( ? ack ? ) after each byte has been received. after the start condition, the i 2 c master sends a chip address. this address is seven bits long followed by an eighth bit which is a data direction bit (r/w). i 2 c_sda i 2 c_scl s p s tart condition sto p condition i 2 c_scl i 2 c_sda data change allowed data change allowed data change allowed data valid data valid
28 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated programming (continued) note according to industry i 2 c standards for 7-bit addresses, the msb of an 8-bit address is removed, and communication actually starts with the 7th most significant bit. for the eighth bit (lsb), a ? 0 ? indicates a write and a ? 1 ? indicates a read. the second byte selects the register to which the data is written. the third byte contains data to write to the selected register. the lp3907 has factory-programmed i 2 c addresses. the wqfn chip has a chip address of 60'h, while the dsbga chip has a chip address of 61'h. figure 41. i 2 c chip address (see note above) w = write (sda = ? 0 ? ) r = read (sda = ? 1 ? ) ack = acknowledge (sda pulled down by either master or slave) rs = repeated start id = lp3907 wqfn chip address: 0x60 ; dsbga chip address: 0x61 figure 42. i 2 c write cycle when a read function is to be accomplished, a write function must precede the read function, as shown in the read cycle waveform. figure 43. i 2 c read cycle ack from slave w ack start msb chip address lsb msb register add lsb msb data lsb ack ack stop ack from slave ack from slave scl start id = k? 60 w ack register addr = k? 10 gdwddgguk? 6a ack ack stop sda rs msb chip address lsb r ack repeated start data from slave ack from master r id = k? 60 ack rs . scl sda start id = k? 60 w ack addr = k? 02 dgguhvvk?$$gdwd ack ack stop ack from slave w ack start msb chip address lsb msb register add lsb msb data lsb ack ack stop ack from slave ack from slave 1 2 3 4 5 6 7 8 9 1 2 3 ... adr6 bit7 msb adr5 bit6 adr4 bit5 adr3 i 2 c slave address (chip address) adr2 bit3 adr1 bit2 adr0 bit1 r/w bit0 lsb 1 1 0 0 0 0 0 bit4
29 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated programming (continued) 8.5.2 factory programmable options table 7 shows options eprom programmed during final test of the lp3907. the system designer that needs specific options is advised to contact the ti sales office. table 7. factory-programmable options factory programmable options current value enable delay for power on code 010 (see control 1 register (scr1) 0x07 ) sw1 ramp speed 8 mv/ s sw2 ramp speed 8 mv/ s the i 2 c chip id address is offered as a metal mask option. the current address for the wqfn chip equals 0x60, while the address for the dsbga chip is 0x61.
30 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.6 register maps 8.6.1 lp3907 control registers register address register name read/write register description 0x02 icra r interrupt status register a 0x07 scr1 r/w system control 1 register 0x10 bkldoen r/w buck and ldo output voltage enable register 0x11 bkldosr r buck and ldo output voltage status register 0x20 vccr r/w voltage change control register 1 0x23 b1tv1 r/w buck1 target voltage 1 register 0x24 b1tv2 r/w buck1 target voltage 2 register 0x25 b1rc r/w buck1 ramp control 0x29 b2tv1 r/w buck2 target voltage 1 register 0x2a b2tv2 r/w buck2 target voltage 2 register 0x2b b2rc r/w buck2 ramp control 0x38 bfcr r/w buck function register 0x39 ldo1vcr r/w ldo1 voltage control registers 0x3a ldo2vcr r/w ldo2 voltage control registers 8.6.1.1 interrupt status register (isra) 0x02 this register informs the system engineer of the temperature status of the chip. d7-d2 d1 d0 name ? temp 125 c ? access ? r ? data reserved status bit for thermal warning pmic t > 125 c 0 ? pmic temp. < 125 c 1 ? pmic temp. > 125 c reserved reset 0 0 0 8.6.1.2 control 1 register (scr1) 0x07 this register allows the user to select the preset delay sequence for power-on timing, to switch between pfm and pwm mode for the bucks, and also to select between an internal and external clock for the bucks. d7 d6-d4 d3 d2 d1 d0 name ? en_dly ? fpwm2 fpwm1 ecen access ? r/w ? r/w r/w r/w data reserved selects the preset delay sequence from en_t assertion (shown below) reserved buck2 pwm /pfm mode select 0 ? auto switch pfm - pwm operation 1 ? pwm mode only buck 1 pwm /pfm mode select 0 ? auto switch pfm - pwm operation 1 ? pwm mode only reserved reset 0 factory-programmed default 1 factory-programmed default factory-programmed default 0
31 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.6.1.3 en_dly preset delay sequence after en_t assertion en_dly < 2:0 > delay (ms) buck1 buck2 ldo1 ldo2 000 1 1 1 1 001 1 1.5 2 2 010 1.5 2 3 6 011 1.5 2 1 1 100 1.5 2 3 6 101 1.5 1.5 2 2 110 3 2 1 1.5 111 2 3 6 11 8.6.1.4 buck and ldo output voltage enable register (bkldoen) ? 0x10 this register controls the enables for the bucks and ldos. d7 d6 d5 d4 d3 d2 d1 d0 name ? ldo2en ? ldo1en ? bk2en ? bk1en access ? r/w ? r/w ? r/w ? r/w data reserved 0 ? disable 1 ? enable reserved 0 ? disable 1 ? enable reserved 0 ? disable 1 ? enable reserved 0 ? disable 1 ? enable reset 0 1 1 1 0 1 0 1 8.6.1.5 buck and ldo status register (bkldosr) ? 0x11 this register monitors whether the bucks and ldos meet the voltage output specifications. d7 d6 d5 d4 d3 d2 d1 d0 name bks_ok ldos_ok ldo2_ok ldo1_ok ? bk2_ok ? bk1_ok access r r r r ? r ? r data 0 ? buck 1-2 not valid 1 ? bucks valid 0 ? ldo 1-2 not valid 1 ? ldos valid 0 ? ldo2 not valid 1 ? ldo2 valid 0 ? ldo1 not valid 1 ? ldo1 valid reserve d 0 ? buck2 not valid 1 ? buck2 valid reserve d 0 ? buck1 not valid 1 ? buck1 valid reset 0 0 0 0 0 0 0 0 8.6.1.6 buck voltage change control register 1 (vccr) ? 0x20 this register selects and controls the output target voltages for the buck regulators. d7-6 d5 d4 d3-2 d1 d0 name ? b2vs b2go ? b1vs b1go access ? r/w r/w ? r/w r/w data reserved buck2 target voltage select 0 ? b2vt1 1 ? b2vt2 buck2 voltage ramp ctrl 0 ? hold 1 ? ramp to b2vs selection reserved buck1 target voltage select 0 ? b1vt1 1 ? b1vt2 buck1 voltage ramp ctrl 0 ? hold 1 ? ramp to b1vs selection reset 00 0 0 00 0 0
32 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.6.1.7 buck1 target voltage 1 register (b1tv1) ? 0x23 this register allows the user to program the output target voltage of buck1. d7-d5 d4-d0 name ? bk1_vout1 access ? r/w data reserved buck1 output voltage (v) 5 ? h00 ext ctrl 5 ? h01 0.80 5 ? h02 0.85 5 ? h03 0.90 5 ? h04 0.95 5 ? h05 1.00 5 ? h06 1.05 5 ? h07 1.10 5 ? h08 1.15 5 ? h09 1.20 5 ? h0a 1.25 5 ? h0b 1.30 5 ? h0c 1.35 5 ? h0d 1.40 5 ? h0e 1.45 5 ? h0f 1.50 5 ? h10 1.55 5 ? h11 1.60 5 ? h12 1.65 5 ? h13 1.70 5 ? h14 1.75 5 ? h15 1.80 5 ? h16 1.85 5 ? h17 1.90 5 ? h18 1.95 5 ? h19 2.00 5 ? h1a ? 5 ? h1f 2.00 reset 000 factory-programmed default
33 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) if using ext ctrl, contact ti sales for support. 8.6.1.8 buck1 target voltage 2 register (b1tv2) ? 0x24 this register allows the user to program the output target voltage of buck1. d7-d5 d4-d0 name ? bk1_vout2 access ? r/w data reserved buck1 output voltage (v) 5 ? h00 ext ctrl (1) 5 ? h01 0.80 5 ? h02 0.85 5 ? h03 0.90 5 ? h04 0.95 5 ? h05 1.00 5 ? h06 1.05 5 ? h07 1.10 5 ? h08 1.15 5 ? h09 1.20 5 ? h0a 1.25 5 ? h0b 1.30 5 ? h0c 1.35 5 ? h0d 1.40 5 ? h0e 1.45 5 ? h0f 1.50 5 ? h10 1.55 5 ? h11 1.60 5 ? h12 1.65 5 ? h13 1.70 5 ? h14 1.75 5 ? h15 1.80 5 ? h16 1.85 5 ? h17 1.90 5 ? h18 1.95 5 ? h19 2.00 5 ? h1a ? 5 ? h1f 2.00 reset 000 factory-programmed default
34 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.6.1.9 buck1 ramp control register (b1rc) - 0x25 this register allows the user to program the rate of change between the target voltages of buck1. d7 d6-d4 d3-d0 name - - - - - - - - b1rs access - - - - - - - - r/w data reserved reserved data code ramp rate mv/us 4h'0 instant 4h'1 1 4h'2 2 4h'3 3 4h'4 4 4h'5 5 4h'6 6 4h'7 7 4h'8 8 4h'9 9 4h'a 10 4h'b - 4h'f 10 reset 0 010 1000
35 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.6.1.10 buck2 target voltage 1 register (b2tv1) ? 0x29 this register allows the user to program the output target voltage of buck2. d7-d5 d4-d0 name ? bk2_vout1 access ? r/w data reserved buck2 output voltage (v) 5 ? h00 ext ctrl 5 ? h01 1.0 5 ? h02 1.1 5 ? h03 1.2 5 ? h04 1.3 5 ? h05 1.4 5 ? h06 1.5 5 ? h07 1.6 5 ? h08 1.7 5 ? h09 1.8 5 ? h0a 1.9 5 ? h0b 2.0 5 ? h0c 2.1 5 ? h0d 2.2 5 ? h0e 2.4 5 ? h0f 2.5 5 ? h10 2.6 5 ? h11 2.7 5 ? h12 2.8 5 ? h13 2.9 5 ? h14 3.0 5 ? h15 3.1 5 ? h16 3.2 5 ? h17 3.3 5 ? h18 3.4 5 ? h19 3.5 5 ? h1a ? 5 ? h1f 3.5 reset 000 factory-programmed default
36 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated (1) if using ext ctrl, contact ti sales for support. 8.6.1.11 buck2 target voltage 2 register (b2tv2) ? 0x2a this register allows the user to program the output target voltage of buck2. d7-5 d4-0 name ? bk2_vout2 access ? r/w data reserved buck2 output voltage (v) 5 ? h00 ext ctrl (1) 5 ? h01 1.0 5 ? h02 1.1 5 ? h03 1.2 5 ? h04 1.3 5 ? h05 1.4 5 ? h06 1.5 5 ? h07 1.6 5 ? h08 1.7 5 ? h09 1.8 5 ? h0a 1.9 5 ? h0b 2.0 5 ? h0c 2.1 5 ? h0d 2.2 5 ? h0e 2.4 5 ? h0f 2.5 5 ? h10 2.6 5 ? h11 2.7 5 ? h12 2.8 5 ? h13 2.9 5 ? h14 3.0 5 ? h15 3.1 5 ? h16 3.2 5 ? h17 3.3 5 ? h18 3.4 5 ? h19 3.5 5 ? h1a ? 5 ? h1f 3.5 reset 000 factory-programmed default
37 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.6.1.12 buck2 ramp control register (b2rc) - 0x2b this register allows the user to program the rate of change between the target voltages of buck2. d7 d6-d4 d3-d0 name - - - - - - - - b2rs access - - - - - - - - r/w data reserved reserved data code ramp rate mv/us 4h'0 instant 4h'1 1 4h'2 2 4h'3 3 4h'4 4 4h'5 5 4h'6 6 4h'7 7 4h'8 8 4h'9 9 4h'a 10 4h'b - 4h'f 10 reset 0 010 1000 8.6.1.13 buck function register (bfcr) ? 0x38 this register allows the buck switcher clock frequency to be spread across a wider range, allowing for less electro-magnetic interference (emi). the spread spectrum modulation frequency refers to the rate at which the frequency ramps up and down, centered at 2 mhz. figure 44. spread spectrum modulation frequency this register also allows dynamic scaling of the npor delay timing. the lp3907 is equipped with an internal por circuit which monitors the output voltage levels on the buck regulators, allowing the user to more actively monitor the power status of the chip. the uvlo feature continuously monitor the raw input supply voltage (vinldo12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 vdc. this prevents the user from damaging the power source (such as battery), but can be disabled if the user wishes. note that if the supply to vdd_m is close to 2.8 v with a heavy load current on the regulators, the chip is in danger of powering down due to uvlo. if the user wishes to keep the chip active under those conditions, enable the bypass uvlo feature. 2 mhz clock frequency time spread spectrum frequency 10 khz triangle wave peak frequency deviation 2 khz triangle wave
38 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated d7-d5 d4 d3-d2 d1 d0 name ? bp_uvlo tpor bk_slomod bk_ssen access ? r/w r/w r/w r/w data reserved bypass uvlo monitoring 0 - allow uvlo 1 - disable uvlo npor delay timing 00 - 50 s 01 - 50 ms 10 - 100 ms 11 - 200 ms buck spread spectrum modulation 0 ? 10 khz triangular wave 1 ? 2 khz triangular wave spread spectrum function output 0 ? disabled 1 ? enabled reset 000 factory-programmed default 01 1 0 8.6.1.14 ldo1 control register (ldo1vcr) ? 0x39 this register allows the user to program the output target voltage of ldo 1. for ? jj11 ? voltage options ldo1 has a fixed output voltage of 2.85 v. d7-d5 d4-d0 name ? ldo1_out access ? r/w data reserved ldo1 output voltage (v) 5 ? h00 1.0 5 ? h01 1.1 5 ? h02 1.2 5 ? h03 1.3 5 ? h04 1.4 5 ? h05 1.5 5 ? h06 1.6 5 ? h07 1.7 5 ? h08 1.8 5 ? h09 1.9 5 ? h0a 2.0 5 ? h0b 2.1 5 ? h0c 2.2 5 ? h0d 2.3 5 ? h0e 2.4 5 ? h0f 2.5 5 ? h10 2.6 5 ? h11 2.7 5 ? h12 2.8 5 ? h13 2.9 5 ? h14 3.0 5 ? h15 3.1 5 ? h16 3.2 5 ? h17 3.3 5 ? h18 3.4 5 ? h19 3.5 5 ? h1a ? 5 ? h1f 3.5 reset 000 factory-programmed default
39 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 8.6.1.15 ldo2 control register (ldo2vcr) ? 0x3a this register allows the user to program the output target voltage of ldo 2. for ? jj11 ? voltage options ldo2 has a fixed output voltage of 2.85 v. d7-d5 d4-d0 name ? ldo2_out access ? r/w data reserved ldo2 output voltage (v) 5 ? h00 1.0 5 ? h01 1.1 5 ? h02 1.2 5 ? h03 1.3 5 ? h04 1.4 5 ? h05 1.5 5 ? h06 1.6 5 ? h07 1.7 5 ? h08 1.8 5 ? h09 1.9 5 ? h0a 2.0 5 ? h0b 2.1 5 ? h0c 2.2 5 ? h0d 2.3 5 ? h0e 2.4 5 ? h0f 2.5 5 ? h10 2.6 5 ? h11 2.7 5 ? h12 2.8 5 ? h13 2.9 5 ? h14 3.0 5 ? h15 3.1 5 ? h16 3.2 5 ? h17 3.3 5 ? h18 3.4 5 ? h19 3.5 5 ? h1a ? 5 ? h1f 3.5 reset 000 factory-programmed default
40 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the lp3907 provides three control methods to turn on/off four power rails: 1. en_t control: provides pre-defined power up/down sequence. (note: v in /battery voltage must be settled approximately 8 ms, minimum, before en_t be asserted high). 2. individual gpio/en pin control: four en pins provide max control flexibility without i 2 c. 3. i 2 c control: besides simple on/off control, also provides access to all the user programmable registers. see register maps for details. 9.2 typical application figure 45. lp3907 typical application 9.2.1 design requirements ten ceramic capacitors and two inductors are required for this application. these three external components must be selected very carefully for property operation. see detailed design procedure . lp3907 vinldo1 sda gnd_l ldo1 enldo1 scl vin1 ldo2 sw2 fb2 vin2 gnd_sw2 ensw1 ensw2 vinldo2 en_t enldo2 gnd_c avdd vinldo12 dap 0.47 p f 1 p f 1 p f 0.47 p f 2.2 p h 10 p f 10 p f 1 p f 1 p f 10 p f gnd_sw1 sw1 fb1 10 p f 2.2 p h npor vdd 100k copyright ? 2016, texas instruments incorporated
41 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated typical application (continued) 9.2.2 detailed design procedure 9.2.2.1 component selection 9.2.2.1.1 inductors for sw1 and sw2 there are two main considerations when choosing an inductor; the inductor must not saturate and the inductor current ripple is small enough to achieve the desired output voltage ripple. care must be taken when reviewing the different saturation current ratings that are specified by different manufacturers. saturation current ratings are typically specified at 25 o c, so ratings at maximum ambient temperature of the application must be requested from the manufacturer. there are two methods to choose the inductor saturation current rating: 9.2.2.1.1.1 method 1: the saturation current is greater than the sum of the maximum load current and the worst case average-to-peak inductor current. this can be written as follows: where ? i ripple = maximum load current ? i outmax = average to peak inductor current ? v in = maximum input voltage to the buck ? l = min inductor value including worse case tolerances (30% drop can be considered for method 1) ? f = minimum switching frequency (1.6 mhz) ? v out = buck output voltage (6) 9.2.2.1.1.2 method 2: a more conservative and recommended approach is to choose an inductor that has saturation current rating greater than the maximum current limit of 1250 ma for buck1 and 1750 ma for buck2. given a peak-to-peak current ripple (i pp ) the inductor needs to be at least (7) space table 8. suggested inductor values inductor value ( h) description notes l sw 1,2 2.2 sw1,2 inductor dcr: 70 m ? 9.2.2.1.2 external capacitors the regulators on the lp3907 require external capacitors for regulator stability. these are specifically designed for portable applications requiring minimum board space and smallest components. these capacitors must be correctly selected for good performance. l t v in - v out i pp x x v out v in 1 ? f 1 ? 1 ? 1 where i ripple = v in - v out 2l x x v out v in 1 ? f 1 ? 1 ? 1 i sat > i outmax + i ripple
42 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 9.2.2.2 ldo capacitor selection 9.2.2.2.1 input capacitor an input capacitor is required for stability. it is recommended that a 1- f capacitor be connected between the ldo input pin and ground (this capacitance value may be increased without limit). this capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. any good quality ceramic, tantalum, or film capacitor may be used at the input. important: tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low impedance source of power (such as a battery or a very large capacitor). if a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. there are no requirements for the equivalent series resistance (esr) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains approximately 1 f over the entire operating temperature range. 9.2.2.2.2 output capacitor the ldos on the lp3907 are designed specifically to work with very small ceramic output capacitors. a 0.47- f ceramic capacitor (temperature types z5u, y5v or x7r) with esr between 5 m ? to 500 m ? , is suitable in the application circuit. it is also possible to use tantalum or film capacitors at the device output, c out (or v out ), but these are not as attractive for reasons of size and cost. the output capacitor must meet the requirement for the minimum value of capacitance and also have an esr value that is within the range 5 m ? to 500 m ? for stability. 9.2.2.2.3 capacitor characteristics the ldos are designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. for capacitance values in the range of 0.47 f to 4.7 f, ceramic capacitors are the smallest, least expensive and have the lowest esr values, thus making them best for eliminating high frequency noise. the esr of a typical 1- f ceramic capacitor is in the range of 20 m ? to 40 m ? , which easily meets the esr requirement for stability for the ldos. for both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. the capacitor value can change greatly, depending on the operating conditions and capacitor type. in particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. the capacitance can vary with dc bias conditions as well as temperature and frequency of operation. capacitor values will also show some decrease over time due to aging. the capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer performance figures in general. as an example, figure 46 is a typical graph comparing different capacitor case sizes.
43 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated figure 46. graph showing typical variation in capacitance vs. dc bias as shown in the graph, increasing the dc bias condition can result in the capacitance value that falls below the minimum value given in the recommended capacitor specifications table. note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. it is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not be suitable in the actual application. the ceramic capacitor ? s capacitance can vary with temperature. the capacitor type x7r, which operates over a temperature range of ? 55 c to 125 c, only varies the capacitance to within 15%. the capacitor type x5r has a similar tolerance over a reduced temperature range of ? 55 c to 85 c. many large value ceramic capacitors, larger than 1 f are manufactured with z5u or y5v temperature characteristics. their capacitance can drop by more than 50% as the temperature varies from 25 c to 85 c. therefore, x7r is recommended over z5u and y5v in applications where the ambient temperature changes significantly above or below 25 c. tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47- f to 4.7- f range. another important consideration is that tantalum capacitors have higher esr values than equivalent size ceramics. this means that while it may be possible to find a tantalum capacitor with an esr value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same esr value. note, also, that the esr of a typical tantalum increases about 2:1 as the temperature goes from 25 c down to ? 40 c, so some guard band must be allowed. 9.2.2.2.4 input capacitor selection for sw1 and sw2 a ceramic input capacitor of 10 f, 6.3 v is sufficient for the magnetic dc-dc converters. place the input capacitor as close to the input of the device as possible. a large value may be used for improved input voltage filtering. the recommended capacitor types are x7r or x5r. y5v type capacitors should not be used. dc bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. the input filter capacitor supplies current to the pfet switch of the dc-dc converter in the first half of each cycle and reduces voltage ripple imposed on the input power source. a ceramic capacitor ? s low esr provides the best noise filtering of the input voltage spikes due to fast current transients. a capacitor with sufficient ripple current rating must be selected. the input current ripple can be calculated as: (8) the worse case is when v in = 2 v out . i rms = i outmax v out v in 1 ? 12 r 2 + 1 (v in v out ) x v out l x f x i outmax x v in where r = 0402, 6.3v, x5r 0603, 10v, x5r 0 1.0 2.0 3.0 4.0 5.0 dc bias (v) 20% 40% 60% 80% 100% cap value (% of nominal 1 p f)
44 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 9.2.2.2.5 output capacitor selection for sw1, sw2 a 10- f, 6.3-v ceramic capacitor must be used on the output of the sw1 and sw2 magnetic dc-dc converters. the output capacitor must be mounted as close to the output of the device as possible. a large value may be used for improved input voltage filtering. the recommended capacitor types are x7r or x5r. y5v type capacitors should not be used. dc bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. dc bias characteristics vary from manufacturer to manufacturer, and dc bias curves should be requested from them and analyzed as part of the capacitor selection process. the output filter capacitor of the magnetic dc-dc converter smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. these capacitors must be selected with sufficient capacitance and sufficiently low esd to perform these functions. the output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its esr and can be calculated as follows: (9) voltage peak-to-peak ripple due to esr can be expressed as follows: v pp ? esr = 2 i ripple r esr (10) because the v pp-c and v pp-esr are out of phase, the rms value can be used to get an approximate value of the peak-to-peak ripple: (11) note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (r esr ). the r esr is frequency dependent as well as temperature dependent. calculate the r esr with the applicable switching frequency and ambient temperature. table 9. suggested capacitor values capacitor min value ( f) description recommended type c ldo1 0.47 ldo1 output capacitor ceramic, 6.3 v, x5r c ldo2 0.47 ldo2 output capacitor ceramic, 6.3 v, x5r c sw1 10 sw1 output capacitor ceramic, 6.3 v, x5r c sw2 10 sw2 output capacitor ceramic, 6.3 v, x5r 9.2.2.2.6 i 2 c pullup resistor both sda and scl pins must have pullup resistors connected to vinldo12 or to the power supply of the i 2 c master. the values of the pullup resistors (typical approximately 1.8 k ? ) are determined by the capacitance of the bus. a resistor that is too large, combined with a given bus capacitance, results in a rise time that would violate the maximum rise time specification. a too-small resistor results in a contention with the pulldown transistor on either slave(s) or master. 9.2.2.3 operation without i 2 c interface operation of the lp3907 without the i 2 c interface is possible if the system can operate with default values for the ldo and buck regulators (see factory programmable options .) the i 2 c-less system must rely on the correct default output values of the ldo and buck converters. 9.2.2.3.1 high v in high-load operation additional information is provided when the ic is operated at extremes of v in and regulator loads. these are described in terms of the junction temperature and, buck output ripple management. 9.2.2.3.2 junction temperature the maximum junction temperature t j-max-op of 125 c of the device package equation 12 through equation 17 demonstrate junction temperature determination, ambient temperature t a-max , and total chip power must be controlled to keep t j below this maximum: v pp-rms = v pp-c 2 + v pp-esr 2 i ripple 4 x f x c v pp-c =
45 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated t j-max-op = t a-max + (r ja ) [ c/ watt] (p d-max ) [watts] (12) total device power dissipation p d-max is the sum of the individual power dissipation of the four regulators plus a minor amount for chip overhead. chip overhead is bias, tsd, and ldo analog. p d-max = p ldo1 + p ld02 + p buck1 + p buck2 + (0.0001a v in ) [watts]. (13) power dissipation of ldo1: p ldo1 = (v inldo1 ? v outldo1 ) i outldo1 [v a] (14) power dissipation of ldo2: p ldo2 = (v inldo2 ? v outldo2 ) i outldo2 [v a] (15) power dissipation of buck1: p buck1 = p in ? p out = v outbuck1 i outbuck1 (1 ? 1 ) / 1 [v a] where ? 1 = efficiency of buck 1 (16) power dissipation of buck2: p buck2 = p in ? p out = v outbuck2 i outbuck2 (1 ? 2 ) / 2 [v a] where ? 2 = efficiency of buck2 where ? is the efficiency for the specific condition taken from efficiency graphs. (17) 9.2.3 application curves v out = 2 v l= 2.2 h figure 47. efficiency vs output current (forced pwm mode) v out = 2 v l= 2.2 h figure 48. efficiency vs output current (pwm-to-pfm mode) output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0.1 1 10 100 1000 v in = 2.8v v in = 3.6v v in = 5.5v output current (ma) efficiency (%) 100 90 80 70 60 50 40 0.1 1 10 100 1000 v = 4.5v in v = 5.5v in
46 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 10 power supply recommendations if the en_t is used to power up the device instead individual ens , then vin must be stable for approximately 8 ms minimum before en_t be asserted high to ensure internal bias, reference, and the flexible por timing are stabilized. this initial en_t delay is necessary only upon first time device power on for power sequencing function to operate properly. 10.1 analog power signal routing all power inputs must be tied to the main vdd source (for example, battery), unless the user wishes to power it from another source. (that is, external ldo output). the analog vdd inputs power the internal bias and error amplifiers, so they must be tied to the main vdd. the analog vdd inputs must have an input voltage between 2.8 v and 5.5 v, as specified in the recommended operating conditions (bucks) table earlier in the data sheet. the other vins (vinldo1, vinldo2) can have inputs lower than 2.8 v, as long as the input it higher than the programmed output (0.3 v). the analog and digital grounds must be tied together outside of the chip to reduce noise coupling.
47 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 11 layout 11.1 dsbga layout guidelines pc board layout is an important part of dc-dc converter design. poor board layout can disrupt the performance of a dc-dc converter and surrounding circuitry by contributing to emi, ground bounce, and resistive voltage loss in the traces. these can send erroneous signals to the dc-dc converter device, resulting in poor regulation or instability. good layout for the lp3907 device bucks can be implemented by following a few simple design rules below. refer to figure 49 for top-layer board buck layout. 1. place the lp3907 bucks, inductor, and filter capacitors close together and make the traces short. the traces between these components carry relatively high switching currents and act as antennas. following this rule reduces radiated noise. special care must be given to place the input filter capacitor very close to the vin and gnd pin. 2. arrange the components so that the switching current loops curl in the same direction. during the first half of each cycle, current flows from the input filter capacitor through the lp3907 bucks and inductor to the output filter capacitor and back through ground, forming a current loop. in the second half of each cycle, current is pulled up from ground through the lp3907 bucks by the inductor to the output filter capacitor and then back through ground forming a second current loop. routing these loops so the current curls in the same direction prevents magnetic field reversal between the two half-cycles and reduces radiated noise. 3. connect the ground pins of the lp3907 bucks and filter capacitors together using generous component-side copper fill as a pseudo-ground plane. then, connect this to the ground-plane (if one is used) with several vias. this reduces ground-plane noise by preventing the switching currents from circulating through the ground plane. it also reduces ground bounce at the lp3907 bucks by giving it a low-impedance ground connection. 4. use wide traces between the power components and for power connections to the dc-dc converter circuit. this reduces voltage errors caused by resistive losses across the traces. 5. route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power components. the voltage feedback trace must remain close to the circuit of the lp3907 buck and must be direct but must be routed opposite to noisy components. this reduces emi radiated onto the dc-dc converter ? s own voltage feedback trace. a good approach is to route the feedback trace on another layer and to have a ground plane between the top layer and layer on which the feedback trace is routed. in the same manner for the adjustable part it is desired to have the feedback dividers on the bottom layer. 6. place noise sensitive circuitry, such as radio if blocks, away from the dc-dc converter, cmos digital blocks and other noisy circuitry. interference with noise-sensitive circuitry in the system can be reduced through distance. for more detailed layout specifications and information, refer to an-1112 dsbga wafer level chip scale package ( snva009 ).
48 lp3907 snvs511s ? june 2007 ? revised april 2016 www.ti.com product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 11.2 layout example figure 49. lp3907 dsbga layout example 11.3 thermal considerations of wqfn package the lp3907 is a monolithic device with integrated power fets. for that reason, it is important to pay special attention to the thermal impedance of the wqfn package and to the pcb layout rules in order to maximize power dissipation of the wqfn package. the wqfn package is designed for enhanced thermal performance and features an exposed die attach pad at the bottom center of the package that creates a direct path to the pcb for maximum power dissipation. compared to the traditional leaded packages where the die attach pad is embedded inside the molding compound, the wqfn reduces one layer in the thermal path. the thermal advantage of the wqfn package is fully realized only when the exposed die attach pad is soldered down to a thermal land on the pcb board with thermal vias planted underneath the thermal land. based on thermal analysis of the wqfn package, the junction-to-ambient thermal resistance (r ja ) can be improved by a factor of two when the die attach pad of the wqfn package is soldered directly onto the pcb with thermal land and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. typical pitch and outer diameter for thermal vias are 1.27 mm and 0.33 mm, respectively. typical copper via barrel plating is 1 oz, although thicker copper may be used to further improve thermal performance. the lp3907 die attach pad is connected to the substrate of the device, and therefore, the thermal land and vias on the pcb board must be connected to ground (gnd pin). for more information on board layout techniques, refer to an ? 1187 leadless lead frame package (llp) ( snoa401 ) on http://www.ti.com . this application note also discusses package handling, solder stencil, and the assembly process.
49 lp3907 www.ti.com snvs511s ? june 2007 ? revised april 2016 product folder links: lp3907 submit documentation feedback copyright ? 2007 ? 2016, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation, see the following: ? an-1112 dsbga wafer level chip scale package ( snva009 ) ? an ? 1187 leadless lead frame package (llp) ( snoa401 ) 12.2 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 12-apr-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lp3907qsq-jjxp/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 07qjjxp lp3907qsq-jxi7/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 07qjxi7 lp3907qsq-jxip/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 07qjxip lp3907qsqx-jjxp/nopb active wqfn rtw 24 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 07qjjxp lp3907qsqx-jxi7/nopb active wqfn rtw 24 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 07qjxi7 lp3907qsqx-jxip/nopb active wqfn rtw 24 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 07qjxip lp3907qtl-vxss/nopb active dsbga yzr 25 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 v025 lp3907qtlx-vxss/nopb active dsbga yzr 25 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 125 v025 lp3907sq-bjx6x/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 07bjx6x lp3907sq-bjxqx/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 07bjxqx lp3907sq-jxqx/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 07-jxqx lp3907sq-pfx6w/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 7pfx6w lp3907sq-pjxix/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 07pjxix lp3907sq-tjxip/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 07tjxip lp3907sq-vrzx/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 07-vrzx lp3907sqx-vrzx/nopb active wqfn rtw 24 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 85 07-vrzx lp3907tl-jj11/nopb active dsbga yzr 25 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 v013
package option addendum www.ti.com 12-apr-2016 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lp3907tl-jjcp/nopb active dsbga yzr 25 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 v016 lp3907tl-jsxs/nopb active dsbga yzr 25 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 v012 lp3907tl-plnto/nopb active dsbga yzr 25 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 v027 lp3907tlx-jj11/nopb active dsbga yzr 25 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 v013 lp3907tlx-jsxs/nopb active dsbga yzr 25 3000 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 v012 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 12-apr-2016 addendum-page 3 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of lp3907, lp3907-q1 : ? catalog: lp3907 ? automotive: lp3907-q1 note: qualified version definitions: ? catalog - ti's standard catalog product ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lp3907qsq-jjxp/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907qsq-jxi7/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907qsq-jxip/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907qsqx-jjxp/nop b wqfn rtw 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907qsqx-jxi7/nopb wqfn rtw 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907qsqx-jxip/nopb wqfn rtw 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907qtl-vxss/nopb dsbga yzr 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 q1 lp3907qtlx-vxss/nop b dsbga yzr 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 q1 lp3907sq-bjx6x/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907sq-bjxqx/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907sq-jxqx/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907sq-pfx6w/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907sq-pjxix/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907sq-tjxip/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907sq-vrzx/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907sqx-vrzx/nopb wqfn rtw 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lp3907tl-jj11/nopb dsbga yzr 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 q1 package materials information www.ti.com 12-apr-2016 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lp3907tl-jjcp/nopb dsbga yzr 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 q1 lp3907tl-jsxs/nopb dsbga yzr 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 q1 lp3907tl-plnto/nopb dsbga yzr 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 q1 lp3907tlx-jj11/nopb dsbga yzr 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 q1 lp3907tlx-jsxs/nopb dsbga yzr 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 q1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lp3907qsq-jjxp/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907qsq-jxi7/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907qsq-jxip/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907qsqx-jjxp/nopb wqfn rtw 24 4500 367.0 367.0 35.0 lp3907qsqx-jxi7/nopb wqfn rtw 24 4500 367.0 367.0 35.0 lp3907qsqx-jxip/nopb wqfn rtw 24 4500 367.0 367.0 35.0 lp3907qtl-vxss/nopb dsbga yzr 25 250 210.0 185.0 35.0 lp3907qtlx-vxss/nopb dsbga yzr 25 3000 210.0 185.0 35.0 lp3907sq-bjx6x/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907sq-bjxqx/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907sq-jxqx/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907sq-pfx6w/nopb wqfn rtw 24 1000 210.0 185.0 35.0 package materials information www.ti.com 12-apr-2016 pack materials-page 2
device package type package drawing pins spq length (mm) width (mm) height (mm) lp3907sq-pjxix/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907sq-tjxip/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907sq-vrzx/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lp3907sqx-vrzx/nopb wqfn rtw 24 4500 367.0 367.0 35.0 lp3907tl-jj11/nopb dsbga yzr 25 250 210.0 185.0 35.0 lp3907tl-jjcp/nopb dsbga yzr 25 250 210.0 185.0 35.0 lp3907tl-jsxs/nopb dsbga yzr 25 250 210.0 185.0 35.0 lp3907tl-plnto/nopb dsbga yzr 25 250 210.0 185.0 35.0 lp3907tlx-jj11/nopb dsbga yzr 25 3000 210.0 185.0 35.0 lp3907tlx-jsxs/nopb dsbga yzr 25 3000 210.0 185.0 35.0 package materials information www.ti.com 12-apr-2016 pack materials-page 3
mechanical da t a r tw0024a www .ti.com s q a 2 4 a ( r e v b )
mechanical data yzr0025xxx www.ti.com tla25xxx (rev d) 0.6000.075 d e a . all linear dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m-1994. b. this drawing is subject to change without notice. notes: 4215055/a 12/12d: max = e: max = 2.521 mm, min = 2.521 mm, min = 2.46 mm2.46 mm
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